1. Field of the Invention
This invention relates to system memory configurations and, more particularly, to the interleaving and de-interleaving of memory.
2. Description of the Related Art
As computer system processors have reached higher performance levels, the need for faster memories has become more evident. However, gains in processor performance have far outpaced gains in memory device performance. Accordingly, various techniques have been employed in an attempt to improve the memory system performance.
For example, in many cases, memory access time may be critical to the satisfactory operation of a particular software application. Depending on the system configuration and size, a computer system may have one or more memory controllers that control multiple banks of memory. In some cases, the way the data is stored in memory may cause bottlenecks. For example, if a particular region or bank of memory is accessed heavily, it may create a bandwidth issue and increase latencies which contribute to degraded system performance.
One technique that is used to improve memory latencies and distribute bandwidth is known as interleaving. Interleaving refers to mapping consecutive cache line addresses to different banks, or in multi-memory controller systems, to different memory controllers. In some systems, each memory controller may include hardware that determines which addresses are mapped to the controller. Thus, the memory controller hardware can be configured to interleave accesses to consecutive cache line addresses.
It may sometimes be desirable to perform a reconfiguration of the memory system. As part of the reconfiguration, a de-interleave operation may sometimes be performed. During a de-interleave operation, the mapping hardware may be reconfigured. In conventional systems, de-interleaving can be a very complex function including multiple address shift cycles, some of which may include varying cycle lengths depending on whether the number of bits in the address is a prime number. For example, to go from an 8-way interleave to a non-interleaved state, it may take a 3-position cyclic shift to the left of the address to get to a first new mapping. Now, the new location already has data in it which needs to be moved to a new position, which causes another 3-position shift, and so on, until all the mappings have been changed and the memory system is in a de-interleaved state.